1. Field of the Invention
This invention relates generally to digital to analog conversion, and more particularly to a system and method for reducing the high data rate of baseband DACs (Digital to Analog Converter) for transmitter applications.
2. Description of the Prior Art
Typical wireless transmitters use a relatively narrow baseband fbw signal sampled at fs rate (for GSM fbw=100 kHz and fs is around 2.16 MHz; for WCDMA fbw=3.84 MHz and fs=15.36 MHz) up-converted at a much larger offset frequency flo (for GSM flo=1.8502-1.9098 GHz; for WCDMA flo=1.92-1.98 GHz). The front-end consists of a Digital-to-Analog Converter (DAC), followed by filtering and up-conversion. The relatively low bandwidth of the baseband signal makes the DAC easily implemented by conventional CMOS structures (mostly current-steering). The output of the DAC is then filtered to remove the image and up-converted in one step (direct conversion) or two steps (super heterodyne) by mixing operations. FIG. 1 is a block diagram illustrating one exemplary direct conversion transmitter 100 that is known in the art. FIG. 2 is a block diagram illustrating one exemplary super heterodyne transmitter 200 that is known in the art.
Some new standards require a much wider baseband signal (for UWB fs=1 GHz) making the implementation of the DAC a difficult task in a pure CMOS process. The power required for analog circuits using CMOS processes, for example, increases exponentially with their required speed.
In view of the foregoing, it is highly desirable and advantageous to provide a scheme for implementing very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS processes allowing an integrated solution with the deep-submicron CMOS digital baseband.